PCB Design Guidelines

Trace and Via Widths

Trace / Via Type Width
(mm) 		Width
(mil) 		Current (A)
Signal Narrow 0.254 10 0.44
Signal 0.381 15 0.59
IC Power Narrow 0.508 20 0.73
IC Power 0.635 25 0.86
IC Power Wide 0.762 30 0.98
Input Power 1.016 40 1.21
Input Power 1.270 50 1.42
Input Power 2.032 80 2.00
Via Small 0.30 / 0.70 12 / 28 0.96
Via 0.40 / 0.80 16 / 32 1.17
Via Large 0.50 / 0.90 20 / 36 1.36
Assumes 1 oz copper layer or 25 μm via plating, and 10 °C temperature rise (IPC-2152).

Trace Current

Current (A) Trace Width
(mm) 		Trace Width
(mil)
0.2 0.085 3.3
0.4 0.221 8.7
0.6 0.386 15.2
0.8 0.574 22.6
1.0 0.781 30.7
2.0 2.033 80.0
4.0 5.288 208.2
6.0 9.251 364.2
8.0 13.76 541.7
10.0 18.72 737.0
Assumes 1 oz copper layer and 10 °C temperature rise (IPC-2152).

Minimum Voltage Clearances

Voltage (V) Internal
Condcutors (mm) 		External
Condcutors (mm)
0 - 30 0.05 0.1
31 - 150 0.1 - 0.2 0.6
151 - 300 0.2 1.25
301 - 500 0.25 2.5
≥ 500 0.25 +
(V - 500) ∙
0.0025 mm/V 		2.5 +
(V - 500) ∙
0.005 mm/V
The values are from the IPC-2221 Generic Standard on Printed Board Design (February 1998).
Spacing between conductors on individual layers should be maximized whenever possible.

Design Rules / Fabrication Capabilities

Parameter Value
Minimum Trace / Space (1 oz Cu) 0.15 mm
(6 mil)
Minimum Trace / Space (2 oz Cu) 0.20 mm
(8 mil)
Minimum Trace to Pad 0.20 mm
(8 mil)
Minimum Trace to Non-plated Hole 0.25 mm
(10 mil)
Copper to Board Edge > 0.38 mm
(15 mil)
Drill Hole Size 0.3 mm - 6.3 mm
(12 mil to 250 mil)
Plated Hole Size 0.2 mm - 6.2 mm
(8 mil to 246 mil)
Minimum Annular Ring Width 0.15 mm
(6 mil)
Min. Via Hole Size / Diameter 0.2 mm / 0.5 mm
(8 mil / 20 mil)
Via Aspect Ratio 6 : 1 typical
8/10 : 1 maximum
Outer Layer Copper Thickness 1 oz / 2 oz
(35 μm / 70 μm)
Inner Layer Copper Thickness 0.5 oz / 1 oz / 2 oz
(17.5 μm / 35 μm / 70 μm)
Minimum Silkscreen Line Width 0.15 mm
(6 mil)
Minimum Silkscreen Character Height 1 mm
(40 mil)
The values are based off standard PCB fabrication capabilities of various PCB vendors.